CHAPTER 3 CPU FUNCTIONS
The CPU of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 is based on the RISC architecture and executes
most instructions in one clock cycle by using a 5-stage pipeline control.
3.1 Features
{ Number of instructions:
83
{ Minimum instruction execution time: 50.0 ns (@ 20 MHz operation, 4.5 to 5.5 V, not using regulator)
62.5 ns (@ 16 MHz operation, 4.0 to 5.5 V, using regulator)
100 ns (@ 10 MHz operation: 2.7 to 5.5 V, not using regulator)
{ Memory space Program space:
64 MB linear
4 GB linear
Data space:
• Memory block division function: 2 MB, 64 KB/Total of 2 blocks (V850ES/KF1)
: 2 MB, 2 MB/Total of 2 blocks (V850ES/KG1)
: 2 MB, 2 MB, 4 MB, 8 MB/Total of 4 blocks (V850ES/KJ1)
{ General-purpose registers: 32 bits × 32
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiply/divide instructions
{ Saturated operation instructions
{ 32-bit shift instruction: 1 clock
{ Load/store instruction with long/short format
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
98
User’s Manual U15862EJ3V0UD
NEC [ NEC ]
