CHAPTER 1 INTRODUCTION
1.4.4 Pin configuration (top view) (V850ES/KJ1)
144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703216GJ-×××-UEN
µPD70F3217GJ-UEN
µPD703217GJ(A)-×××-UEN
µPD703217YGJ(A)-×××-UEN
µPD70F3217GJ(A)-UEN
µPD70F3217YGJ(A)-UEN
µPD703216YGJ-×××-UEN
µPD703217GJ-×××-UEN
µPD70F3217YGJ-UEN
µPD703216GJ(A)-×××-UEN
µPD703216YGJ(A)-×××-UEN
µPD703217YGJ-×××-UEN
AVREF0
AVSS
P10/ANO0
P11/ANO1
AVREF1
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BVDD
BVSS
PCT7
PCT6/ASTB
PCT5
PCT4/RD
PCT3
P00/TOH0
P01/TOH1
PPNote 1/ICNote 1
V
VDD
9
REGC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
V
SS
X1
X2
RESET
XT1
XT2
PCT2
PCT1/WR1
PCT0/WR0
PCS7
PCS6
PCS5
PCS4
PCM5
PCM4
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PCS3/CS3
PCS2/CS2
PCS1/CS1
PCS0/CS0
PCD3
PCD2
PCD1
PCD0
P915/A15/INTP6
P914/A14/INTP5
P913/A13/INTP4
P912/A12/SCKA1
P02/NMI
P03/INTP0
P04/INTP1
P05/INTP2
P06/INTP3
P40/SI00
P41/SO00
P42/SCK00
P30/TXD0
P31/RXD0
P32/ASCK0
P33/TI000/TO00
P34/TI001
P35/TI010/TO01
P36
P37
EVSS
EVDD
P38/SDA0Note 2
P39/SCL0Note 2
74
73
Notes 1. IC: Connect directly to VSS (µPD703216, 703216Y, 703217, 703217Y).
VPP: Connect to VSS in normal operation mode (µPD70F3217, 70F3217Y).
2. SCL0, SDA0, SCL1, and SDA1 can be used only for the µPD703216Y, 703217Y, and 70F3217Y.
Caution Make EVDD the same potential as VDD.
BVDD can be used when VDD = EVDD ≥ BVDD.
User’s Manual U15862EJ3V0UD
49
NEC [ NEC ]
