CHAPTER 1 INTRODUCTION
1.4 V850ES/KJ1
1.4.1 Features (V850ES/KJ1)
{ Number of instructions: 83
{ Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set: Signed multiplication (16 × 16 → 32): 1 to 2 clocks
(Instructions without creating register hazards can be continuously executed in parallel)
Saturated operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space: 64 MB of linear address space
Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB (Total of 4 blocks)
{ External bus interface
16-bit data bus
Address bus: Separate output possible
{ Internal memory
µPD703216, 703216Y (Mask ROM: 96 KB/RAM: 6 KB)
µPD703217, 703217Y (Mask ROM: 128 KB/RAM: 6 KB)
µPD70F3217, 70F3217Y (Flash memory: 128 KB/RAM: 6 KB)
{ Interrupts and exceptions
Non-maskable interrupts: 3 sources
Maskable interrupts:
43 sources (µPD703216, 703217, 70F3217)
45 sources (µPD703216Y, 703217Y, 70F3217Y)
Software exceptions:
Exception trap:
Total: 128
32 sources
1 source
{ I/O lines:
{ Key interrupt function
{ Timer/counter
16-bit timer/event counter: 6 channels
8-bit timer/event counter: 2 channels
8-bit timer H: 2 channels
{ Watch timer: 1 channel
{ Watchdog timers
Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel
Watchdog timer 2: 1 channel
{ Serial interface (SIO)
Asynchronous serial interface (UART): 3 channels
3-wire serial I/O (CSI0): 3 channels
3-wire serial I/O (with automatic transmit/receive function) (CSIA): 2 channels
I2C bus interface (I2C): 2 channels
(µPD703216Y, 703217Y, 70F3217Y)
{ A/D converter: 10-bit resolution × 16 channels
{ D/A converter: 8-bit resolution × 2 channels
{ Real-time output port: 6 bit × 2 channels
{ Power-save functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes
User’s Manual U15862EJ3V0UD
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NEC [ NEC ]
