CHAPTER 1 INTRODUCTION
1.2.4 Pin configuration (top view) (V850ES/KF1)
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD703208GC-×××-8BT
µPD703208YGC-×××-8BT
µPD703208GK-×××-9EU
µPD703208YGK-×××-9EU
µPD703209GC-×××-8BT
µPD703209YGC-×××-8BT
µPD703208GK(A)-×××-9EU
µPD703208YGK(A)-×××-9EU
µPD703209GC(A)-×××-8BT
µPD703209YGC(A)-×××-8BT
µPD703209GK(A)-×××-9EU
µPD703209YGK(A)-×××-9EU
µPD703209GK-×××-9EU
µPD70F3210GC-8BT
µPD70F3210YGC-8BT
µPD70F3210GK-9EU
µPD70F3210YGK-9EU
µPD703208GC(A)-×××-8BT
µPD703208YGC(A)-×××-8BT
µPD70F3210GK(A)-9EU
µPD70F3210YGK(A)-9EU
µPD703209YGK-×××-9EU
µPD703210GC-×××-8BT
µPD703210YGC-×××-8BT
µPD703210GK-×××-9EU
µPD703210YGK-×××-9EU
µPD703210GC(A)-×××-8BT
µPD703210YGC(A)-×××-8BT
µPD703210GK(A)-×××-9EU
µPD703210YGK(A)-×××-9EU
µPD70F3210GC(A)-8BT
µPD70F3210YGC(A)-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVREF0
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PDL3/AD3
AVss
P00/TOH0
PDL2/AD2
PDL1/AD1
P01/TOH1
PDL0/AD0
P02/NMI
PCT6/ASTB
PCT4/RD
P03/INTP0
P04/INTP1
PPNote 1/ICNote 1
PCT1/WR1
PCT0/WR0
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PCS1/CS1
PCS0/CS0
P915/INTP6
P914/INTP5
P913/INTP4
P99/SCK01
P98/SO01
V
V
DD
REGC
10
11
12
13
14
15
16
17
18
19
20
V
SS
X1
X2
RESET
XT1
XT2
P05/INTP2
P06/INTP3
P40/SI00
P41/SO00
P97/SI01
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Notes 1. IC: Connect directly to VSS (µPD703208, 703208Y, 703209, 703209Y, 703210, 703210Y).
VPP: Connect to VSS in normal operation mode (µPD70F3210, 70F3210Y).
2. SCL0 and SDA0 can be used only for the µPD703208Y, 703209Y, 703210Y, and 70F3210Y.
Caution Make EVDD the same potential as VDD.
User’s Manual U15862EJ3V0UD
33
NEC [ NEC ]
