CHAPTER 1 INTRODUCTION
1.2.5 Function block configuration (V850ES/KF1)
(1) Internal block diagram
ROM
CPU
NMI
INTC
16-bit
timer/event
counter: 2 ch
Instruction
queue
INTP0 to INTP6
PC
Note 1
HLDRQ
HLDAK
ASTB
RD
32-bit barrel
shifter
Multiplier
16 × 16→32
TI000, TI001,TI010, TI011
RAM
TO00, TO01
System
registers
WAIT
BCU
Note 2
WR0, WR1
CS0, CS1
ALU
8-bit
timer/event
counter: 2 ch
TI50, TI51
General-purpose
registers
32 bits × 32
TO50, TO51
AD0 to AD15
ROM
correction
8-bit timer H:
2 ch
TOH0, TOH1
SIO
CLKOUT
Ports
A/D
SO00, SO01
SI00, SI01
SCK00, SCK01
X1
converter
CSI0: 2 ch
X2
CG
XT1
XT2
RESET
SOA0
SIA0
SCKA0
CSIA: 1 ch
SDA0Note 3
SCL0Note 3
I2CNote 3
: 1 ch
V
DD
Regulator
TXD0, TXD1
RXD0, RXD1
ASCK0
ICNote 4
EVDD
EVSS
UART: 2 ch
Note 5
V
V
PP
Key interrupt
function
Watchdog
timer
KR0 to KR7
SS
Watch timer
RTP00 to RTP05
RTP: 1 ch
Notes 1. µPD703208, 703208Y:
µPD703209, 703209Y:
64 KB (mask ROM)
96 KB (mask ROM)
128 KB (mask ROM)
µPD703210, 703210Y:
µPD70F3210, 70F3210Y: 128 KB (flash memory)
2. µPD703208, 703208Y, 703209, 703209Y: 4 KB
µPD703210, 703210Y, 70F3210, 70F3210Y: 6 KB
3. Only for the µPD703208Y, 703209Y, 703210Y, and 70F3210Y
4. Only for the µPD703208, 703208Y, 703209, 703209Y, 703210, and 703210Y
5. Only for the µPD70F3210 and 70F3210Y
User’s Manual U15862EJ3V0UD
35
NEC [ NEC ]
