CHAPTER 1 INTRODUCTION
(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other types of instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter
(32 bits) help accelerate processing of complex instructions.
(b) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory space and the CPU does not send a bus cycle start
request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched
instruction code is stored in an internal instruction queue.
(c) ROM
This consists of a 128 KB, 96 KB, or 64 KB mask ROM or flash memory mapped to the address spaces
from 0000000H to 001FFFFH, 0000000H to 0017FFFH, or 0000000H to 000FFFFH, respectively.
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
This consists of a 6 KB or 4 KB RAM mapped to the address spaces from 3FFD800H to 3FFEFFFH or
3FFE000H to 3FFEFFFH, respectively.
RAM can be accessed by the CPU in one clock cycle during data access.
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed for interrupt sources.
(f) Clock generator (CG)
The clock generator includes two types of oscillators: one for the main clock (fXX) and one for the subclock
(fXT). It generates seven types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT), and supplies one of
them as the operating clock for the CPU (fCPU).
(g) Timer/counter
Two 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated,
enabling measurement of pulse intervals and frequency as well as programmable pulse output.
Two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer.
Two 8-bit timer H channels are provided on chip.
(h) Watch timer
This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz)
or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an
interval timer.
User’s Manual U15862EJ3V0UD
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NEC [ NEC ]
