LIST OF FIGURES (6/6)
Figure No.
Title
Page
19-4
Maskable Interrupt Servicing......................................................................................................................623
RETI Instruction Processing.......................................................................................................................624
Example of Interrupt Nesting......................................................................................................................626
Example of Servicing Simultaneously Generated Interrupt Requests........................................................628
Software Exception Processing..................................................................................................................643
RETI Instruction Processing.......................................................................................................................644
Exception Trap Processing ........................................................................................................................647
Processing Flow for Restore from Exception Trap.....................................................................................647
Debug Trap Processing..............................................................................................................................648
Processing Flow for Restore from Debug Trap ..........................................................................................649
Pipeline Operation During Interrupt Request Acknowledgment (Outline)...................................................652
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
20-1
Key Return Block Diagram.........................................................................................................................654
21-1
21-2
Status Transition ........................................................................................................................................657
Oscillation Stabilization Time .....................................................................................................................665
22-1
22-2
22-3
Reset Block Diagram..................................................................................................................................671
Hardware Status on RESET Input..............................................................................................................674
Operation on Power Application.................................................................................................................674
23-1
23-2
Regulator....................................................................................................................................................675
REGC Pin Connection................................................................................................................................676
24-1
24-2
Block Diagram of ROM Correction.............................................................................................................677
ROM Correction Operation and Program Flow ..........................................................................................680
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
25-10
25-11
25-12
25-13
25-14
Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-80GC-8BT, FA-80GK-9EU)..........................683
Wiring Example of V850ES/KG1 Flash Writing Adapter (FA-100GC-8EU)................................................685
Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) .................................................687
Environment for Writing Program to Flash Memory ...................................................................................688
Communication with Dedicated Flash Programmer (UART0) ....................................................................688
Communication with Dedicated Flash Programmer (CSI00)......................................................................689
Communication with Flash Programmer (CSI00+HS)................................................................................689
Example of Connection of VPP Pin .............................................................................................................691
Signal Collision (Input Pin of Serial Interface) ............................................................................................692
Malfunction of Other Device.......................................................................................................................693
Signal Collision (RESET Pin) .....................................................................................................................694
Flash Memory Manipulation Procedure......................................................................................................695
Flash Memory Programming Mode............................................................................................................696
Communication Commands.......................................................................................................................697
24
User’s Manual U15862EJ3V0UD
NEC [ NEC ]
