LIST OF FIGURES (2/6)
Figure No.
Title
Page
4-34
4-35
4-36
4-37
4-38
4-39
4-40
Block Diagram of PCM4 and PCM5...........................................................................................................233
Block Diagram of PCS0 to PCS3 ...............................................................................................................238
Block Diagram of PCS4 to PCS7 ...............................................................................................................239
Block Diagram of PCT0, PCT1, PCT4, and PCT6 .....................................................................................244
Block Diagram of PCT2, PCT3, PCT5, and PCT7 .....................................................................................245
Block Diagram of PDH0 to PDH7...............................................................................................................250
Block Diagram of PDL0 to PDL15..............................................................................................................254
5-1
Data Memory Map (V850ES/KF1)..............................................................................................................266
Data Memory Map (V850ES/KG1).............................................................................................................267
Data Memory Map (V850ES/KJ1)..............................................................................................................268
Little Endian Address in Word....................................................................................................................271
Example of Inserting Wait States ...............................................................................................................279
Multiplex Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) ..................................................................285
Multiplex Bus Read Timing (Bus Size: 8 Bits) ............................................................................................285
Multiplex Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)...................................................................286
Multiplex Bus Write Timing (Bus Size: 8 Bits) ............................................................................................286
Multiplex Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)....................................................................287
Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access)..................................................................288
Separate Bus Read Timing (Bus Size: 8 Bits)............................................................................................288
Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) ..................................................................289
Separate Bus Write Timing (Bus Size: 8 Bits)............................................................................................289
Separate Bus Hold Timing (Bus Size: 8 Bits, Write)...................................................................................290
Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access)...........................................290
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
6-1
Clock Generator.........................................................................................................................................293
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Block Diagram of 16-Bit Timer/Event Counter 0n.......................................................................................304
Control Register Setting Contents During Interval Timer Operation...........................................................320
Configuration of Interval Timer...................................................................................................................320
Timing of Interval Timer Operation.............................................................................................................321
Control Register Settings in PPG Output Operation...................................................................................323
Configuration of PPG Output......................................................................................................................324
PPG Output Operation Timing ...................................................................................................................325
Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register .........................................................................................................................327
Configuration for Pulse Width Measurement with Free-Running Counter..................................................327
Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register
7-9
7-10
(with Both Edges Specified) .......................................................................................................................328
Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter..................329
CR0n1 Capture Operation with Rising Edge Specified ..............................................................................330
Timing of Pulse Width Measurement with Free-Running Counter (with Both Edges Specified).................330
Control Register Settings for Pulse Width Measurement with Free-Running Counter
7-11
7-12
7-13
7-14
and Two Capture Registers........................................................................................................................331
20
User’s Manual U15862EJ3V0UD
NEC [ NEC ]
