LIST OF TABLES (2/4)
Table No.
Title
Page
5-7
6-1
Bus Priority.................................................................................................................................................284
Operation Status of Each Clock .................................................................................................................299
7-1
7-2
7-3
7-4
Configuration of 16-Bit Timer/Event Counters 00 to 05..............................................................................303
Valid Edge of TI0n0 Pin and Capture Trigger of CR0n0 Register ..............................................................305
Valid Edge of TI0n1 Pin and Capture Trigger of CR0n0 Register ..............................................................305
Valid Edge of TI0n0 Pin and Capture Trigger of CR0n1 Register ..............................................................307
8-1
9-1
Configuration of 8-Bit Timer/Event Counters 50 and 51.............................................................................351
Configuration of 8-Bit Timers H0 and H1....................................................................................................369
10-1
10-2
10-3
10-4
Configuration of RTO .................................................................................................................................393
Operation During Manipulation of Real-Time Output Buffer Registers n....................................................393
Operation Modes and Output Triggers of Real-Time Output Port (n = 0)...................................................395
Operation Modes and Output Triggers of Real-Time Output Port (n = 1, V850ES/KJ1 only).....................395
11-1
11-2
11-3
Interval Time of Interval Timer....................................................................................................................401
Configuration of Watch Timer.....................................................................................................................402
Interval Time of Interval Timer....................................................................................................................404
12-1
12-2
12-3
12-4
12-5
Configuration of Watchdog Timer 1............................................................................................................410
Program Loop Detection Time of Watchdog Timer 1 .................................................................................414
Interval Time of Interval Timer....................................................................................................................415
Configuration of Watchdog Timer 2............................................................................................................417
Watchdog Timer 2 Clock Selection ............................................................................................................418
13-1
13-2
13-3
Configuration of A/D Converter ..................................................................................................................421
Operation Mode Control.............................................................................................................................424
A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) ...........................431
14-1
Configuration of D/A Converter ..................................................................................................................437
15-1
15-2
15-3
15-4
Generated Interrupts and Default Priorities................................................................................................452
Reception Error Causes.............................................................................................................................461
Baud Rate Generator Setting Data ............................................................................................................469
Maximum and Minimum Allowable Baud Rate Error..................................................................................471
16-1
16-2
SCK0n Pin Output Status...........................................................................................................................500
SO0n Pin Output Status.............................................................................................................................500
17-1
17-2
Configuration of CSIAn...............................................................................................................................502
Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values .........................509
26
User’s Manual U15862EJ3V0UD
NEC [ NEC ]
