LIST OF TABLES (3/4)
Table No.
Title
Page
17-3
17-4
17-5
17-6
17-7
Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values.........................509
CSIA0 Buffer RAM.....................................................................................................................................511
CSIA1 Buffer RAM.....................................................................................................................................512
Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values.........................526
Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values.........................526
18-1
18-2
18-3
18-4
18-5
18-6
Configuration of I2Cn..................................................................................................................................548
Selection Clock Setting..............................................................................................................................562
INTIICn Generation Timing and Wait Control.............................................................................................589
Extension Code Bit Definitions...................................................................................................................591
Status During Arbitration and Interrupt Request Generation Timing..........................................................592
Wait Periods...............................................................................................................................................593
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
Interrupt Source List (V850ES/KF1)...........................................................................................................608
Interrupt Source List (V850ES/KG1)..........................................................................................................610
Interrupt Source List (V850ES/KJ1)...........................................................................................................612
NMI Valid Edge Specification.....................................................................................................................621
Interrupt Control Registers (xxlCn) (V850ES/KF1).....................................................................................630
Interrupt Control Registers (xxlCn) (V850ES/KG1)....................................................................................631
Interrupt Control Registers (xxlCn) (V850ES/KJ1).....................................................................................632
INTP0 to INTP3 Pins Valid Edge Specification ..........................................................................................641
INTP4 to INTP6 Pins Valid Edge Specification ..........................................................................................642
20-1
Assignment of Key Return Detection Pins .................................................................................................654
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
Standby Modes..........................................................................................................................................656
Operation After Releasing HALT Mode by Interrupt Request ....................................................................659
Operation Status in HALT Mode ................................................................................................................660
Operation After Releasing IDLE Mode by Interrupt Request......................................................................661
Operation Status in IDLE Mode .................................................................................................................662
Operation After Releasing STOP Mode by Interrupt Request....................................................................663
Operation Status in STOP Mode................................................................................................................664
Operation Status in Subclock Operation Mode ..........................................................................................667
Operation After Releasing Sub-IDLE Mode by Interrupt Request..............................................................668
Operation Status in Sub-IDLE Mode..........................................................................................................669
22-1
22-2
Hardware Status on RESET Pin Input or Occurrence of WDTRES2 .........................................................673
Hardware Status on Occurrence of WDTRES1 .........................................................................................673
24-1
Correspondence Between CORCN Register Bits and CORADn Registers ...............................................679
25-1
25-2
25-3
Wiring Between µPD70F3210 and 70F3210Y (V850ES/KF1), and PG-FP3 .............................................682
Wiring Between µPD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3.............................................684
Wiring Between µPD70F3217 and 70F3217Y (V850ES/KJ1), and PG-FP3..............................................686
27
User’s Manual U15862EJ3V0UD
NEC [ NEC ]
