LIST OF FIGURES (4/6)
Figure No.
Title
Page
12-1
12-2
Block Diagram of Watchdog Timer 1..........................................................................................................409
Block Diagram of Watchdog Timer 2..........................................................................................................416
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
Block Diagram of A/D Converter ................................................................................................................420
Operation Sequence ..................................................................................................................................424
Relationship Between Analog Input Voltages and A/D Conversion Results...............................................427
Power Fail Monitoring Function (PFCM = 0) ..............................................................................................429
Timing of A/D Converter Sampling and A/D Conversion Start Delay .........................................................430
Overall Error...............................................................................................................................................432
Quantization Error......................................................................................................................................433
Zero-Scale Error.........................................................................................................................................433
Full-Scale Error ..........................................................................................................................................434
Differential Linearity Error...........................................................................................................................434
Integral Linearity Error................................................................................................................................435
Sampling Time ...........................................................................................................................................435
14-1
Block Diagram of D/A Converter ................................................................................................................436
15-1
Selecting Mode of UART2 or I2C1..............................................................................................................441
Block Diagram of Asynchronous Serial Interface n ....................................................................................444
Format of Asynchronous Serial Interface Transmit/Receive Data..............................................................453
Asynchronous Serial Interface Transmission Completion Interrupt Timing ................................................455
Continuous Transmission Processing Flow................................................................................................457
Continuous Transmission Starting Procedure............................................................................................458
Continuous Transmission End Procedure..................................................................................................459
Asynchronous Serial Interface Reception Completion Interrupt Timing .....................................................461
When Reception Error Interrupt Is Separated from INTSRn Interrupt (ISRMn Bit = 0)...............................462
When Reception Error Interrupt Is Included in INTSRn Interrupt (ISRMn Bit = 1)......................................462
Noise Filter Circuit......................................................................................................................................464
Timing of RXDn Signal Judged as Noise ...................................................................................................464
Configuration of Baud Rate Generator n (BRGn).......................................................................................465
Allowable Baud Rate Range During Reception..........................................................................................470
Transfer Rate During Continuous Transmission ........................................................................................472
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
Block Diagram of Clocked Serial Interface.................................................................................................476
Timing Chart in Single Transfer Mode........................................................................................................486
Timing Chart According to Clock Phase Selection.....................................................................................488
Timing Chart of Interrupt Request Signal Output in Delay Mode................................................................490
Repeat Transfer (Receive-Only) Timing Chart...........................................................................................493
Repeat Transfer (Transmission/Reception) Timing Chart ..........................................................................495
Timing Chart of Next Transfer Reservation Period.....................................................................................496
Transfer Request Clear and Register Access Conflict ...............................................................................498
Interrupt Request and Register Access Conflict.........................................................................................499
22
User’s Manual U15862EJ3V0UD
NEC [ NEC ]
