µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(4) SRAM, external ROM, external I/O access timing
(a) Access timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
<16> tDKA
Condition
Unit
ns
MIN.
2
MAX.
10
Address, CSn output delay time (from
CLKOUT ↓)
Address, CSn output hold time (from
<17>
<18>
<19>
<20>
<21>
<22>
<23>
tHKA
2
2
2
2
2
2
2
10
14
14
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
CLKOUT ↓)
RD, IORD ↓ delay time
(from CLKOUT ↑)
tDKRDL
tHKRDH
tDKWRL
tHKWRH
tDKBSL
tHKBSH
RD, IORD ↑ delay time
(from CLKOUT ↑)
UWR, LWR, IOWR ↓ delay time (from
CLKOUT ↑)
UWR, LWR, IOWR ↑ delay time (from
CLKOUT ↑)
BCYST ↓ delay time (from CLKOUT
↓)
BCYST ↑ delay time (from CLKOUT
↓)
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
<24>
<25>
<26>
tSWK
tHKW
tSKID
10
2
ns
ns
ns
Data input setup time
10
(to CLKOUT ↑)
Data input hold time
<27>
<28>
<29>
tHKID
tDKOD
tHKOD
2
2
2
ns
ns
ns
(from CLKOUT ↑)
Data output delay time
10
10
(from CLKOUT ↓)
Data output hold time
(from CLKOUT ↓)
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID.
2. n = 0 to 7
80
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
