µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(a) Access timing (SRAM, external ROM, external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
<16>
<22>
<17>
A0 to A23 (Output)
CSn (Output)
<23>
BCYST (Output)
<18>
<20>
<19>
RD, IORD (Output)
[Read time]
<21>
<27>
UWR, LWR, IOWR (Output)
[Write time]
<26>
D0 to D15 (I/O)
[Read time]
<28>
<29>
D0 to D15 (I/O)
[Write time]
<25>
<25>
<24>
<24>
WAIT (Input)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
81
Preliminary Data Sheet U14168EJ2V0DS00