µPD31172
(a) Serial BAUDOUT timing
CLK
(internal, 1.8462 MHz)
t
BLD
t
HW
t
BHD
BAUDOUTB
(1 cycle) (internal)
t
LW
t
t
t
BLD
BLD
BLD
t
BHD
t
t
HW
BAUDOUTB
(2 cycles) (internal)
t
LW
HW
t
BHD
BAUDOUTB
(3 cycles) (internal)
t
LW
t
BHD
t
HW
BAUDOUTB
(N cycles, N > 3)
(internal)
t
LW
(b) Serial receive timing
RCLK
(BAUDOUTB)
t
SCD
8 RCLKC
16 RCLKC
Internal sample clock
Start bit
Parity bit Stop bit
RXD (input)
DATA (5:8)
Internal sample clock
INTRP (output)
tSINT
(receive data existence interruptNote 1
)
INTRP (output)
(receive status interruptNote 2
)
t
RINT2
IOR# (input)
(reading RBR register)
tRINT1
IOR# (input)
(reading LSR register)
Notes 1. Dependant on the existence of receive data. At this time, bit 0 of the IER register is 1, and bits 3 to
1 of the IIR register are 0, 1, 0, respectively.
2. Dependant on the receive line status. At this time, bit 2 of the IER register is 1, and bits 3 to 1 of the
IIR register are 0, 1, 1, respectively.
28
Data Sheet U14388EJ2V0DS00
NEC [ NEC ]
