µPD31172
(9) 16550-compatible serial interface parameters
Parameter
Symbol
N
Conditions
MIN.
1
TYP.
MAX.
Unit
Transmit clock division ratio
2
16 − 1
10
Transmit clock rising edge delay time (from CLKNote 1
)
tBHD
tBLD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transmit clock falling edge delay time (from CLKNote 1
)
15
Transmit clock pulse low-level width
tLW
N = 1
N = 2
N = 3
N > 3
N = 1
N = 2
N = 3
N > 3
0.5CLKC
1CLKC
2CLKC
2CLKC
0.5CLKC
1CLKC
1CLKC
Transmit clock pulse high-level width
tHW
(N − 2)
CLKC
Interrupt cancellation time (from IOR# ↑, when reading
tRINT1
40
30
10
ns
ns
LSR register)
Interrupt cancellation time (from IOR# ↓, when reading
tRINT2
RBR register)
Sample clock delay time (from RCLK)
tSCD
tSINT
ns
ns
Interrupt generation time (from valid data reception,
reception error)
1 RCLKC
+ 20Note 2
Interrupt cancellation time (from IOW# ↓, when writing to
tHR
30
ns
ns
ns
ns
ns
ns
ns
ns
THR register)
Interrupt cancellation time (from IOR# ↑, when reading
tIR
40
IIR register)
Transmission start time
tIRS
8 BAUC
24 BAUC
+ 20
Interrupt generation time (from IOW# ↑, when writing to
tSI
16 BAUC
24 BAUC
+ 20
THR register)
Interrupt generation time (from stop bit)
tSTI
tMDO
tRIM
tSIM
8 BAUC +
20
RTS#, DTR delay time (from IOW# ↑, when writing to
30
30
30
MCR register)
Interrupt cancellation time (from IOR# ↓, when reading
MSR register)
Interrupt cancellation time (from RI# ↑, CTS#, DSR#,
DCD#)
Notes 1. CLK is the internal system clock of the 16550 serial controller, and has a frequency of 1.8462 MHz.
2. When bit 0 of the FCR register is 1, tSINT = 3 RCLKC + 20 (ns).
During a timeout interrupt, tSINT = 8 RCLKC + 20 (ns).
Remark CLKC:
RCLKC:
CLK (internal system clock of 16550 serial controller) cycle
RCLK (on-chip serial controller receive clock) cycle
BAUDOUTB (on-chip serial controller transmit clock) cycle
BAUC:
RCLKC = BAUC in this case.
27
Data Sheet U14388EJ2V0DS00
NEC [ NEC ]
