CHAPTER 12 SERIAL INTERFACE 20
(1) Transmission shift register 20 (TXS20)
TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20
bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data
to TXS20 triggers transmission.
TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS20 to FFH.
Caution Do not write to TXS20 during transmission.
TXS20 and reception buffer register 20 (RXB20) are mapped at the same address, such
that any attempt to read from TXS20 results in a value being read from RXB20.
(2) Reception shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one
entire byte has been received, RXS20 feeds the reception data to reception buffer register 20 (RXB20).
RXS20 cannot be manipulated directly by a program.
(3) Reception buffer register 20 (RXB20)
RXB20 holds a reception data. A new reception data is transferred from reception shift register 20 (RXS20)
every 1-byte data reception.
When the data length is seven bits, the reception data is sent to bits 0 to 6 of RXB20, in which the MSB is
always fixed to 0.
RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written.
RESET input makes RXB20 undefined.
Caution RXB20 and transmission shift register 20 (TXS20) are mapped at the same address, such
that any attempt to write to RXB20 results in a value being written to TXS20.
(4) Transmission controller
The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the
data in transmission shift register 20 (TXS20), according to the setting of asynchronous serial interface
mode register 20 (ASIM20).
(5) Reception controller
The reception controller controls reception according to the setting of asynchronous serial interface mode
register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is
detected, asynchronous serial interface status register 20 (ASIS20) is set according to the status of the
error.
User’s Manual U15075EJ1V0UM00
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NEC [ NEC ]
