DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low
periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit
may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be
synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period
(even if the entry ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the
response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from
the start of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is
assumed that there was no Refresh command in progress when Idle state was entered.
Transition period for short CKE cycles with entry and exit period overlapping
(AL=0; WL=5; tANPD=WL-1=4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK
CK
CMD
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
tANPD
tANPD
tXPDLL
PD exit transition period
PD entry transition period
tRFC(min)
CKE
Short CKE high transition period
tXPDLL
Do not
care
Transitioning
Version 2.3
02/2017
86
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