DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
Synchronous to asynchronous transition during Precharge Power Down (with DLL
frozen) entry (AL=0; CWL=5; tANPD=WL-1=4)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
CK
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CMD
CKE
tCPDEDmin
tANPD
tCPDED
PD entry transition period
Last sync.
ODT
tAOFmin
RTT
RTT
tAOFmax
ODTLoff
Sync. Or
async. ODT
RTT
RTT
tAOFPDmin
tAOFPDmax
ODTLoff+tAOFPDmin
ODTLoff+tAOFPDmax
First async.
ODT
tAOFPDmax
RTT
RTT
tAOFPDmin
Do not
care
Time
Break
Transitioning
Version 2.3
02/2017
83
Nanya Technology Cooperation ©
All Rights Reserved.