DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
DDR3L Allowed time before ringback (tDVAC) for CK - and DQS -
DDR3L-800/1066/1333/1600
DDR3L-1866
tDVAC [ps]
Slew Rate
[V/ns]
tDVAC [ps]
@|VIH/Ldiff(AC)| =
320 mV
tDVAC [ps]
@|VIH/Ldiff(AC)| =
270 mV
tDVAC [ps]
@|VIH/Ldiff(AC)| =
270 mV
tDVAC [ps]
@|VIH/Ldiff(AC)| =
260 mV
@|VIH/Ldiff(AC)| =
250 mV
Min
189
189
162
109
91
Max
Min
201
201
179
134
119
100
76
Max
Min
163
163
140
95
Max
Min
168
168
147
105
91
Max
Min
176
176
154
111
97
Max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
80
1.6
69
62
74
78
1.4
40
37
52
56
1.2
note
note
note
44
5
22
24
1.0
note
note
note
note
note
note
note
note
< 1.0
NOTE 1. Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become
equal to or less than VILdiff(ac) level.
Version 2.3
02/2017
100
Nanya Technology Cooperation ©
All Rights Reserved.
NANYA [ Nanya Technology Corporation. ]
