DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3(L)
SDRAM. In this operation, the DDR3(L) SDRAM allows a read or write command (either with or without auto-precharge) to
be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is
issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings.
Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL
register options are shown as the following table.
Additive Latency (AL) Settings
A4
A3
AL
0, (AL Disable)
CL-1
0
0
0
1
1
0
CL-2
1
1
Reserved
Version 2.3
02/2017
23
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