NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
ODT Timing Diagrams
Dynamic ODT: Behavior with ODT being asserted before and after the write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK
CK
CMD
NOP
NOP
NOP
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
ODT
ODTLoff
ODTH4
tAOFmin
ODTLcwn4
tADCmin
tADCmin
tAONmin
RTT_Nom
RTT_WR
RTT_Nom
RTT
tAOFmax
tAONmax
tADCmax
tADCmax
ODTLon
ODTLcnw
ODTH4
DQS/DQS
WL
Din
n
Din
n+1
Din
n+2
Din
n+3
DQ
Do not
care
Transitioning
Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write
command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command).
Dynamic ODT: Behavior without write command, AL=0, CWL=5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
CMD
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
ODT
ODTLoff
ODTLoff
ODTH4
tADCmin
tAONmin
RTT_Nom
RTT
tADCmax
tAONmax
ODTLon
DQS/DQS
DQ
Do not
care
Transitioning
Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at
T5 would also be legal.
Version 1.4
05/2019
73
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