NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
Dynamic ODT: Behavior with ODT pin being asserted together with write command
for the duration of 6 clock cycles.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
CMD
NOP
WRS8
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
ODTLon
Address
ODT
ODTH8
ODTLoff
tAOFmin
tAONmin
RTT_WR
RTT
tAOFmax
tAONmax
ODTLcwn8
DQS/DQS
WL
Din
h
Din
h+1
Din
h+2
Din
h+3
Din
h+4
Din
h+5
Din
h+6
Din
h+7
DQ
Do not
care
Transitioning
Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied.
Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF),
AL=0, CWL=5.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
ODTLcnw
CMD
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
ODT
ODTH4
tAONmin
ODTLoff
tADCmin
tAOFmin
RTT_WR
RTT_Nom
tADCmax
RTT
tAOFmax
tAONmax
ODTLon
ODTLcwn4
DQS/DQS
WL
Din
n
Din
n+1
Din
n+2
Din
n+3
DQ
Do not
care
Transitioning
Version 1.4
05/2019
74
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