NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the
DDR3(L) SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As
the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or
re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be
altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the
user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be
redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which mean
these commands can be executed any time after power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the
minimum time required between two MRS commands shown as below.
tMRD Timing
CK
CK
CMD
ADDR
CKE
MRS
VAL
NOP
NOP
NOP
NOP
MRS
VAL
tMRD
Do not
Care
Time break
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset,
and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the
following figure.
Version 1.4
05/2019
13
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