NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
Reset and Initialization Sequence at Power- on Ramping (Cont’d)
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
tCKSRX
CK
CK
RESET
CKE
10ns
tIS
Valid
Valid
Valid
Valid
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
ODT
NOP*
MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
NOP*
Command
BA0-BA2
VDD,
VDDQ
tDLLK
tMRD
T=200us
tXPR
tMRD
tMRD
tMOD
T=500us
tZQinit.
Do Not
Care
Time break
* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.
Reset Procedure at Stable Power (Cont’d)
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to
be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3 (L) SDRAM is ready for normal operation.
Reset Procedure at Power Stable Condition
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
tCKSRX
CK
CK
RESET
CKE
10ns
tIS
Valid
Valid
Valid
Valid
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
ODT
NOP*
MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
NOP*
Command
BA0-BA2
VDD,
VDDQ
tDLLK
tMRD
T=100ns
tXPR
tMRD
tMRD
tMOD
T=500us
tZQinit.
Do Not
Care
Time break
* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.
Version 1.4
05/2019
11
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