Operational Overview
MU9C4320L ATMCAM
The VP Table contains 4K entries, corresponding to the 12
bits in the VPI field of the ATM header. In a multiple
device system, only the lowest-priority device holds the
VP Table. A hit in the VP Table takes lower priority than a
match in the CAM array where the VPI/VCI fields are
compared associatively. If there is a mismatch in the CAM
array, but a hit in the VP Table, the VPI value is driven
onto the Address Output bus. Flags indicate whether a
CAM match or VP Table hit has occurred.
reset either with an address or an associative match.
Therefore, when a new VPI/VCI entry is written to the
CAM, its Validity bit is set valid.
When a connection is removed, the Validity bit for that
entry is reset, and the address of the location is driven onto
the Active Address bus. This simple mechanism allows
easy maintenance of the connection list in both the CAM
array and the external RAM.
The ATMCAM supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the
slight timing overhead associated with the daisy chain is
unacceptable in the fastest systems, the ATMCAM is
designed to facilitate external prioritization across
multiple devices.
The VP Table eliminates the need to do two sequential
compares, one on the full VPI/VCI fields, and the other on
the VPI fields. The test of both sets of fields is
accomplished by the ATMCAM in a single compare cycle.
The validity of a location in the CAM array is determined
by an extra bit called the Validity bit. This bit is set and
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