Electrical
MU9C4320L ATMCAM
Switching Characteristics
-70
-90
-12
No
1a
1b
2a
2b
3
Symbol
tELEL
tELEL
tELEH
tELEH
tEHEL
tCVEL
tELCX
tELQX
tELQV
Parameter (all times in nanoseconds)
Chip Enable Cycle Time (Short Cycle)
Chip Enable Cycle Time (Compare Cycle)
Chip Enable LOW Pulse Width (Short Cycle)
Chip Enable LOW Pulse Width (Compare Cycle)
Chip Enable HIGH Pulse Width
Min Max Min Max Min Max Notes
50
70
40
60
10
5
50
90
40
75
10
8
75
120
55
90
10
10
5
3
4
3
4
4
Control Input to Chip Enable LOW Setup Time
Control Input to Chip Enable LOW Hold Time
Chip Enable LOW to Outputs Active
5
5
6
6
6
7
6
5
3
3
6
5
5
5
7
Chip Enable LOW to Outputs Valid
Register
Memory
40
50
10
40
70
10
50
80
15
8
tEHQZ
tDVEL
Chip Enable HIGH to Outputs High-Z
Data to Chip Enable LOW Setup Time
Data from Chip Enable LOW Hold Time
Full In Valid to Chip Enable LOW Setup Time
Full In Valid to Full Flag Valid
2
3
3
0
2
3
3
0
2
5
5
3
9
10
11
12
13
14
15
16
17
18
19
tELDX
tFIVEL
tFIVFFV
tEHFFV
tEHQX
tEHQV
tMIVEL
tEHMX
tEHMV
tMIVMV
8
9
12
25
Chip Enable HIGH to Full Flag Valid
Chip Enable HIGH to Output Change
Chip Enable HIGH to Output Valid
16
16
2
2
2
22
25
30
Match In Valid to Chip Enable LOW Setup
Chip Enable HIGH to Match Flag Change
Chip Enable HIGH to Match Flag Valid
Match In Valid to Match Flag Valid
8
2
10
2
12
2
17
8
20
9
25
12
/MF, /MV
/MM
10
10
12
10
10
14
12
15
16
20
21
22
23
24
tOEHQZ
tOELQV2
tMIVOEL
tFIVOEL
tEHRSTL
Output Enable HIGH to Outputs High-Z
Output Enable LOW to Match Address Outputs Valid
Match in Valid to Output Enable LOW
Full in Valid to Output Enable LOW
2
2
2
3
3
4
3
3
4
Chip Enable HIGH to Reset LOW
20
50
20
20
20
2
20
50
20
20
20
2
25
70
25
25
25
2
25 tRSTLRSTH Reset Pulse Width
8
26
27
28
tRSTHEL
Reset HIGH to Chip Enable LOW
tTIVTCLKH Test Input Valid to TCLK HIGH Setup Time
tTCLKHTIX TCLK HIGH to Test Input Hold Time
9
9
29 tTCLKLTDOX TCLK LOW to TDO Change
30 tTCLKLTDOV TCLK LOW to TDO Valid
31 tTCLKLTDOZ TCLK LOW to TDO High-Z
10
20
10
20
15
25
20
20
25
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
-1.0V for a duration of 10ns measured from the 50% amplitude points for input-only lines.
Common I/O lines are clamped so that transients cannot fall below -0.5V.
Applies to all cycle types except Compare cycles and Memory Read cycles.
Applies to Compare cycles.
Control signals are /CS1, /CS2, /W, /AV, and AC11–0.
With loads specified in Figure 5.
With loads specified in Figure 6.
/E should be HIGH during /RESET active to ensure proper device defaults.
Test inputs are the TDI and TMS signals.
10. With output and I/O pins unloaded.
11. Pins with internal pull-ups are /RESET, TCLK, TMS, TDI, and /TRST.
Rev. 3
29
MUSIC [ MUSIC SEMICONDUCTORS ]
