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MU9C2485A-90TCI 参数 Datasheet PDF下载

MU9C2485A-90TCI图片预览
型号: MU9C2485A-90TCI
PDF下载: 下载PDF文件 查看货源
内容描述: WidePort LANCAM㈢家庭 [WidePort LANCAM㈢ Family]
分类和应用: 局域网
文件页数/大小: 28 页 / 161 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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WidePort LANCAM® Family  
OPERATIONAL CHARACTERISTICS Continued  
/E  
/W  
/CM  
/EC  
DQ15–0  
DATA OUT  
Figure 3: Read Cycle  
/E  
/W  
/CM  
DQ15–0  
Figure 4: Write Cycle  
ASS OCIATED DATA  
READ CYCLE  
STATUS READ  
CYCLE  
COM PARAND W RITE  
CYCLE  
/E  
/CM  
/W  
DQ31–0  
DATA  
DATA  
DATA  
/EC  
/M F  
MATCH FLAG VALID  
/MA, /MM  
/M F FL AGS UPD A TED  
Figure 5: Cycle to Cycle Timing Example  
of the Comparand Write cycle, assuming /EC is LOW at the  
start of this cycle. Data writes and reads to the comparand,  
mask registers or memory occur in one or two 32-bit cycles,  
depending on the settings in the Segment Control register.  
The Compare operation automatically occurs during Data  
writes to the Comparand or mask registers when the  
destination segment counter reaches the end count set in  
the Segment Control register. If there was a match, the  
second cycle reads status or associated data, depending  
on the state of /CM. For cascaded devices, /EC needs to be  
LOW at the start of the cycle prior to any cycle that requires  
a locked daisy chain, such as a Status register or associated  
data read after a match. If there is no match in Standard  
mode, the output buffers stay HIGH-Z, and the daisy chain  
must be unlocked by taking /EC HIGH during a NOP or  
other non-functioning cycle, as indicated in Table 6a.  
Figure 6 shows how the internal /EC timing holds the daisy  
chain locking effect over into the next cycle. In the Enhanced  
mode, this NOP is not needed before data or command  
writes following a non-matching compare, as indicated by  
Table 6b. A single-chip system does not require daisy-  
chained match flag operation, hence /EC could be tied HIGH  
and the /MA pin or flag in the Status register used instead  
of /MF, allowing access to the device regardless of the  
match condition.  
The minimum timings for the /E control signal are given in  
the Switching Characteristics section. Note that at minimum  
timings the /E signal is non-symmetrical, and that different  
cycle types have different timing requirements, as given in  
Table 8.  
13  
Rev. 2  
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