WidePort LANCAM® Family
OPERATIONAL CHARACTERISTICS Continued
CAM Status
/RESET Condition
Skip = 0, Empty = 1 (empty)
Enabled
Validity bits at all memory locations
Match and Full flag outputs
IEEE 802.3-802.5 Input Translation
CAM/RAM Partitioning
Not Translated
64 bits CAM, 0 bits RAM
Disabled
Comparison Masking
Address register auto-increment or -decrement
Source and Destination Segment counters count ranges
Address register and Next Free Address register
Page Address and Device Select registers
Control register after reset (including CT15)
Persistent Destination for Command writes
Persistent Source for Command reads
Persistent Source and Destination for Data reads and writes
Operating Mode
Disabled
0B to 1B; loaded with 0B
Contain all 0s
Contain all 0s (no change on Software reset)
Contains 0008H
Instruction decoder
Status register
Comparand register
Standard
Configuration Register set
Foreground
Table 5: Device Control State after Reset
contained in the Address register. After the execution of the
instruction, the Address register will increment, decrement, or
stay the same value depending on the setting of Control
Register bits CT3 and CT2.
Next Free address. Additionally, writes to the Page Address
register will be disabled. All other instructions operate
normally. Additionally, with the /FF disabled, /FF=/FI.
Normal operation of the device is with the /FF enabled. The
Full Flag Enable field has no effect on the /FL Status Register
bit. This bit always reflects the true state of the device.
Control Register (CT)
The Control register is composed of a number of switches
that configure the WidePort LANCAM, as shown in Table
9. It is written or read through DQ15–0 using a TCO CT
instruction on DQ31–16. On read cycles, DQ31–16 will be
the upper 16 bits of the Status register. If bit 15 of the value
written during a TCO CT is a 0, the device is reset (and all
other bits are ignored). See Table 5 for the Reset states. Bit
15 always reads back as a 0. A write to the Control register
causes an automatic compare to occur (except in the case
of a reset). Either the Foreground or Background Control
register will be active, depending on which register set has
been selected, and only the active Control register will be
written to or read from.
The IEEE Translation control at bits 10 and 9 can be used
to enable the translation hardware for writes to 64-bit
resources in the device. When translation is enabled, the
bits are reordered as shown in Figure 2.
Control Register bits 8–6 control the CAM/RAM
partitioning. The CAM portion of each word may be sized
from a full 64 bits down to 16 bits in 16-bit increments. The
RAM portion can be at either end of the 64-bit word.
Compare masks may be selected by bits 5 and 4. Mask
Register 1, Mask Register 2, or neither may be selected to
mask compare operations. The address register behavior is
controlled by bits 3 and 2, and may be set to increment,
decrement, or neither after a memory access. Bits 1 and 0
set the operating mode: Standard (compatible with the
MU9C1485) as shown in Table 6a, or Enhanced as shown
in Table 6b. The device will reset to the Standard mode and
follow the operating responses in Table 6a. When operating
If the Match flag is disabled through bits 14 and 13, the
internal match condition, /MA(int), used to determine a
daisy-chained device’s response is forced HIGH as shown
in Tables 6a and 6b, so that Case 6 is not possible,
effectively removing the device from the daisy chain. With
the Match flag disabled, /MF=/MI and operations directed
to Highest-priority Match locations are ignored. Normal
operation of the device is with the /MF enabled. The Match
Flag Enable field has no effect on the /MA or /MM output
pins or Status Register bits. These bits always reflect the
true state of the device.
DQ31
DQ24 DQ23
DQ16 DQ15
DQ8 DQ7
DQ0
DQ31
DQ24 DQ23
DQ16 DQ15
DQ8 DQ7
DQ0
If the Full Flag is disabled through bits 12 and 11, the
device behaves as if it were full and ignores instructions to
Figure 2: IEEE 802.3/802.5 Format Mapping
9
Rev. 2
MUSIC [ MUSIC SEMICONDUCTORS ]
