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MU9C2485A-90TCI 参数 Datasheet PDF下载

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型号: MU9C2485A-90TCI
PDF下载: 下载PDF文件 查看货源
内容描述: WidePort LANCAM㈢家庭 [WidePort LANCAM㈢ Family]
分类和应用: 局域网
文件页数/大小: 28 页 / 161 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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WidePort LANCAM® Family  
OPERATIONAL CHARACTERISTICS Continued  
Case  
Internal  
/EC(int)  
Internal  
/MA (int)  
External  
/MI  
Device Select Command Data Write Command Data Read  
Reg.  
Write1  
Read  
1
2
3
1
1
1
X
X
X
X
X
X
DS=FFFFH  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
NO  
YES  
NO  
NO  
YES  
NO  
DS=PA  
DSFFFFH and  
DSPA  
4
5
62  
0
0
0
X
1
0
0
1
1
X
X
X
NO  
NO  
YES3  
NO  
NO  
YES4  
NO5  
NO5  
YES5  
NO  
NO  
YES  
Table 6a: Standard Mode Device Select Response  
Case  
Internal  
/EC(int)  
Internal  
/MA (int)  
External  
/MI  
Device Select  
Reg.  
Command Data Write Command Data Read  
Write1  
Read  
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH  
DS = PA  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
NO  
YES  
NO  
NO  
YES  
NO  
DS FFFFH  
and DS PA  
4
5
62  
0
0
0
0
1
0
0
X
1
X
X
X
YES3,6  
YES3,6  
YES3  
YES4,7  
YES4,7  
YES4  
NO5  
NO5  
YES5  
NO  
NO  
YES  
Table 6b: Enhanced Mode Device Select Response  
NOTES:  
1. Exceptions are:  
A) A write to the Device Select register is always active in all devices;  
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and  
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.  
2. If /MF is disabled in the Control register, /MA (Internal) is forced HIGH preventing a Case 6 response.  
3. This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.  
4. This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.  
5. For a Command Read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain  
(for example, /FI LOW and /FF HIGH) and NO if it does not.  
6. This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.  
7. This is NO if the Persistent Destination is Memory at Highest-Priority match.  
empty memory locations. Bits 28 and 27 are the Skip and Empty  
Validity bits, which reflect the validity of the last memory  
location read. After a reset, the Skip and Empty bits will read  
11 until a read or move from memory has occurred. The rest of  
the Status register contains the Page address of the device  
and the address of the Highest-Priority match. After a reset or  
a no-match condition, the match address bits will be all 1s.  
Select register to the value of the desired device’s Page  
address and leaving /EC HIGH.  
The Full Flag daisy chain causes only the device whose /FI  
input is LOW and /FF output HIGH to respond to an  
instruction using the Next Free address. After a reset, the  
Next Free Address register is set to zero.  
Comparand Register (CR)  
Status Register  
The 64-bit Comparand register is the default destination  
for data writes and reads, using the Segment Control register  
to select which of the two 32-bit segments of the Comparand  
register is to be loaded or read out. The persistent source  
and destination for data writes and reads can be changed  
to the mask registers or memory by SPS and SPD  
The 32-bit Status register, shown in Table 12, is the default  
source for Command Read cycles. Bit 31 is the internal Match  
flag, which will go LOW if a match was found in this particular  
device. Bit 30 is the internal Multiple Match flag, which will go  
LOW if a Multiple match was detected. Bit 29 is the internal  
Full flag, which will go LOW if the particular device has no  
11  
Rev. 2  
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