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MU9C2485A-90TCI 参数 Datasheet PDF下载

MU9C2485A-90TCI图片预览
型号: MU9C2485A-90TCI
PDF下载: 下载PDF文件 查看货源
内容描述: WidePort LANCAM㈢家庭 [WidePort LANCAM㈢ Family]
分类和应用: 局域网
文件页数/大小: 28 页 / 161 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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WidePort LANCAM® Family  
OPERATIONAL CHARACTERISTICS Continued  
instructions. During an automatic or forced compare, the  
Comparand register is simultaneously compared against  
the CAM portion of all memory locations with the correct  
validity condition. Automatic compares always compare  
against valid memory locations, while forced compares,  
using CMP instructions, can compare against memory  
locations tagged with any specific validity condition.  
THE MEMORY ARRAY  
Memory Organization  
The Memory array is organized into 64-bit words with each  
word having an additional two validity bits (Skip and  
Empty). By default, all words are configured to be 64 CAM  
cells. However, bits 8–6 of the Control register can divide  
each word into a CAM field and a RAM field. The RAM  
field can be assigned to the least-significant or most-  
significant portion of each entry. The CAM/RAM  
partitioning is allowed on 16-bit boundaries, permitting  
selection of the configurations shown in Table 9, bits 8–6  
(e.g., “001” sets the 48 MSBs to CAM and the 16 LSBs to  
RAM). Memory Array bits designated as RAM can be used  
to store and retrieve data associated with the CAM content  
at the same memory location.  
The Comparand register may be shifted one bit at a time to  
the right or left by issuing a Shift Right or Shift Left  
instruction, with the right and left limits for the wrap-around  
determined by the CAM/RAM partitioning set in the Control  
register. During shift rights, bits shifted off the LSB of the  
CAM partition will reappear at the MSB of the CAM  
partition. Likewise, bits shifted off the MSB of the CAM  
partition will reappear at the LSB during shift lefts.  
Mask Registers (MR1, MR2)  
Memory Access  
The Mask registers can be used in two different ways, either  
to mask compares or to mask data writes and moves. Either  
mask register can be selected in the Control register to  
mask every compare, or selected by instructions to  
participate in data writes or moves to and from Memory. If  
a bit in the selected mask register is set to a 0, the  
corresponding bit in the Comparand register will enter into  
a masked compare operation. If a Mask bit is a 1, the  
corresponding bit in the Comparand register will not enter  
into a masked compare operation. Bits set to 0 in the mask  
register cause corresponding bits in the destination register  
or memory location to be updated when masking data writes  
or moves, while a bit set to 1 will prevent that bit in the  
destination from being changed.  
There are two general ways to get data into and out of the  
memory array: directly or by moving the data through the  
Comparand or mask registers.  
The first way, through direct reads or writes, is set up by  
issuing a Set Persistent Destination (SPD) or Set Persistent  
Source (SPS) command. The addresses for the direct access  
can be directly supplied, supplied from the Address register,  
supplied from the Next Free Address register, or supplied  
as the Highest-Priority Match address. Additionally, all the  
direct writes can be masked by either mask register.  
The second way is to move data via the Comparand or  
mask registers. This is accomplished by issuing Data Move  
commands (MOV). Moves using the Comparand register  
can also be masked by either of the mask registers.  
Either the Foreground or Background MR1 can be set  
active, but after a reset, the Foreground MR1 is active  
by default. MR2 incorporates a sliding mask, where the  
data can be replicated one bit at a time to the right or left  
with no wrap-around by issuing a Shift Right or Shift  
Left instruction. The right and left limits are determined  
by the CAM/RAM partitioning set in the Control register.  
For a Shift Right the upper limit bit is replicated to the  
next lower bit, while for a Shift Left the lower limit bit is  
replicated to the next higher bit.  
I/O CYCLES  
The WidePort LANCAM supports four basic I/O cycles: Data  
Read, Data Write, Command Read, and Command Write. The  
type of cycle is determined by the states of the /W and /CM  
control inputs. These signals are registered at the beginning  
of a cycle by the falling edge of /E. Table 3 shows how the /W  
and /CM lines select the cycle type and how the data bus is  
utilized for each.  
During Read cycles, the DQ31–0 outputs are enabled after  
/E goes LOW. During Write cycles, the data or command  
to be written is captured from DQ31–0 at the beginning of  
the cycle by the falling edge of /E. Figures 3 and 4 show  
Read and Write cycles respectively. Figure 5 shows typical  
cycle-to-cycle timing with the Match flag valid at the end  
Rev. 2  
12  
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