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MU9C2485A-90TCI 参数 Datasheet PDF下载

MU9C2485A-90TCI图片预览
型号: MU9C2485A-90TCI
PDF下载: 下载PDF文件 查看货源
内容描述: WidePort LANCAM㈢家庭 [WidePort LANCAM㈢ Family]
分类和应用: 局域网
文件页数/大小: 28 页 / 161 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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WidePort LANCAM® Family  
OPERATIONAL CHARACTERISTICS Continued  
in Enhanced mode, it is not necessary to unlock the daisy  
chain with a NOP instruction before command or data writes  
after a non-matching compare, as required in Standard mode.  
Device Select Register (DS)  
The Device Select register is used to select a specific (target)  
device using the TCO DS instruction in DQ31–16 and  
setting the 16-bit DS value in DQ15–0 equal to the target’s  
PA value. The DS register can be read through DQ15–0  
with DQ31–16 returning the upper 16 bits of the Status  
register. In a daisy chain, setting DS = FFFFH will select all  
devices. However, in this case, the ability to read information  
out of the device is restricted as shown in Tables 6a and 6b.  
A software reset (using the Control register) does not affect  
the Device Select register.  
Segment Control Register (SC)  
The Segment Control register, as shown in Table 10, is  
accessed using a TCO SC instruction with the register contents  
placed on DQ15–0. On read cycles, DQ31–16 will be the upper  
16 bits of the Status register, and D15, D10, D5, and D2 always  
read back as 0s. Reserved locations D14, D12, D9, D7, D4, and  
D1 should always be set to 0 and as such will also read back as  
0s. Either the Foreground or Background Segment Control  
register will be active, depending on which register set has  
been selected, and only the active Segment Control register  
will be written to or read from.  
Address Register (AR)  
The Address register points to the CAM memory location  
to be operated upon when a M@[AR] or M@aaaH is part  
of the instruction. It can be loaded directly by using a TCO  
AR instruction or indirectly by using an instruction requiring  
an absolute address, such as MOV aaaH, CR,V. The AR  
register can be read through DQ15–0 with DQ31–16  
returning the upper 16 bits of the Status register. After  
being loaded, the Address register value will then be used  
for the next memory access referencing the Address register.  
A reset sets the Address register to zero.  
The Segment Control register contains dual independent  
incrementing counters with limits, one for data reads and  
one for data writes. These counters control which 32-bit  
segment of the 64-bit internal resource is accessed during  
a particular data cycle on the 32-bit data bus. The actual  
destination for data writes and source for data reads (called  
the persistent destination and source) are set independently  
with SPD and SPS instructions, respectively.  
Control Register bits CT3 and CT2 set the address to  
automatically increment or decrement (or not change)  
during sequences of Command or Data cycles. The Address  
register will change after executing an introduction that  
includes M@[AR] or M@aaaH, or after a data access to  
the end limit segment (as set in the Segment Control  
register) when the persistent source or destination is  
M@[AR] or M@aaaH.  
Each of the two counters consists of a start limit, an end  
limit, and the current segment pointer, each a single bit  
representing either the lower segment (0) or the upper  
segment (1). The current segment pointer can be set to  
either 0 or 1 even if that value is outside the range set by  
the start and end segments. The counters count up from  
the current segment pointer to the end limit and then roll  
over back to the start limit.  
Either the Foreground or Background Address register will  
be active, depending on which register set has been  
selected, and only the active Address register will be written  
to or read from.  
If a sequence of data writes or reads is interrupted, the  
Segment Control register can be reset to its initial start limit  
values with the RSC instruction. After a reset, both Source  
and Destination counters are set to count from Segment 0  
to Segment 1 with an initial value of 0.  
Next Free Address Register (NF)  
The WidePort LANCAM automatically stores the address  
of the first empty memory location in the Next Free Address  
register, which is then used as a memory address pointer  
for M@NF operations. The Next Free Address register,  
shown in Table 11, can be read through DQ15–0 using a TCO  
NF instruction. DQ31–16 will return the upper 16 bits of the  
Status register. By taking /EC LOW during the TCO NF  
instruction cycle, only the device with /FI LOW and /FF  
HIGH will output the contents of its Next Free Address  
register, which gives the Next Free address in a system of  
daisy-chained devices. The Next Free address may be read  
from a specific device in the chain by setting the Device  
Page Address Register (PA)  
The Page Address register is loaded using a TCO PA  
instruction on DQ31–16 with a user selected 16-bit value  
(not FFFFH) on DQ15–0. During reads of the PA register,  
DQ31–16 will all be 0. The entry in the PA register is used to  
give a unique address to the different devices in a daisy  
chain. In a daisy chain, the PA value of each device is  
loaded using the SFF instruction to advance to the next  
device, as shown in the “Setting Page Address Register  
Values” section. A software reset (using the Control  
register) does not affect the Page Address register.  
Rev. 2  
10  
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