Instruction Set Summary
LANCAM B Family
Instruction: Data Move (continued)
Instruction: Validity Bit Control
Operation
Mnemonic
Op-Code
Operation
Mnemonic
Op-Code
Mask Register 2 from:
Comparand Register
Mask Register 1
Set Validity bits at Address Register
Set Valid
MOV MR2,CR
MOV MR2,MR1
NOP
0310H
0311H
0312H
0314H
0B14H
0315H
VBC [AR],V
VBC [AR],E
VBC [AR],S
VBC [AR],R
0424H
0425H
0426H
0427H
Set Empty
No Operation
Set Skip
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match
MOV MR2,[AR]
MOV MR2,aaaH
MOV MR2,HM
Set Random Access
Set Validity bits at Address
Set Valid
VBC aaaH,V
VBC aaaH,E
VBC aaaH,S
VBC aaaH,R
0C24H
0C25H
0C26H
0C27H
Memory at Address Register, No Change to Validity bits, from:
Set Empty
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV [AR],CR
0320H
0360H
03A0H
0321H
0322H
Set Skip
MOV [AR],CR[MR1]
MOV [AR],CR[MR2]
MOV [AR],MR1
MOV [AR],MR2
Set Random Access
Set Validity bits at Highest-Priority Match
Set Valid
VBC HM,V
042CH
042DH
042EH
042FH
Set Empty
VBC HM,E
VBC HM,S
VBC HM,R
Memory at Address Register, Location set Valid, from:
Set Skip
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV [AR],CR,V
0324H
0364H
03A4H
0325H
0326H
Set Random Access
MOV [AR],CR[MR1],V
MOV [AR],CR[MR2],V
MOV [AR],MR1,V
MOV [AR],MR2,V
Set Validity bits at All Matching Locations
Set Valid
VBC ALM,V
043CH
043DH
043EH
043FH
Set Empty
VBC ALM,E
VBC ALM,S
VBC ALM,R
Set Skip
Memory at Address, No Change to Validity bits, from:
Set Random Access
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV aaaH0,CR
0B20H
0B60H
0BA0H
0B21H
0B22H
MOV aaaH,CR[MR1]
MOV aaaH,CR[MR2]
MOV aaaH,MR1
Instruction: Compare
Operation
Mnemonic
CMP V
Op-Code
0504H
MOV aaaH,MR2
Compare Valid Locations
Compare Empty Locations
Compare Skipped Locations
Comp. Random Access Locations
Memory at Address, Location set Valid, from:
CMP E
0505H
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV aaaH,CR,V
0B24H
0B64H
0BA4H
0B25H
0B26H
CMP S
0506H
MOV aaaH,CR[MR1],V
MOV aaaH,CR[MR2],V
MOV aaaH,MR1,V
CMP R
0507H
MOV aaaH,MR2,V
Instruction: Special Instructions
Memory at Highest-Priority Match, No Change to Validity bits, from:
Operation
Mnemonic
Op-Code
0600H
0601H
0610H
0611H
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV HM,CR
0328H
0368H
03A8H
0329H
032AH
Shift Comparand Right
Shift Comparand Left
SFT CR, R
SFT CR, L
SFT M2, R
SFT M2, L
SFR
MOV HM,CR[MR1]
MOV HM,CR[MR2]
MOV HM,MR1
Shift Mask Register 2 Right
Shift Mask Register 2 Left
Select Foreground Registers
Select Background Registers
Reset Seg. Cont. Reg. to Initial Val.
MOV HM,MR2
0618H
0619H
061AH
Memory at Highest-Priority Match, Location set Valid, from:
SBR
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV HM,CR,V
032CH
036CH
03ACH
032DH
032EH
RSC
MOV HM,CR[MR1],V
MOV HM,CR[MR2],V
MOV HM,MR1,V
MOV HM,MR2,V
Instruction: Miscellaneous
Operation
No Operation
Set Full Flag
Mnemonic
NOP
Op-Code
0300H
Memory at Next Free Address, No Change to Validity bits, from:
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV NF,CR
0330H
0370H
03B0H
0331H
0332H
SFF
0700H
MOV NF,CR[MR1]
MOV NF,CR[MR2]
MOV NF,MR1
MOV NF,MR2
Memory at Next Free Address, Location set Valid, from:
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
MOV NF,CR,V
0334H
0374H
03B4H
0335H
0336H
MOV NF,CR[MR1],V
MOV NF,CR[MR2],V
MOV NF,MR1,V
MOV NF,MR2,V
Rev. 5.1
21
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