Operational Characteristics
LANCAM B Family
Vertically Cascaded System Initialization
initialization, all devices are empty, thus the top device in
the string responds to a TCO PA instruction, and loads its
PA register. A Set Full Flag (SFF) instruction advances to
the next device in the string and is active only for the
device with /FI LOW and /FF HIGH. The SFF instruction
changes the first device’s /FF to LOW, although the device
really is empty, which allows the next device in the string
to respond to the TCO PA instruction and load its PA
register. The initialization proceeds through the chain in a
similar manner filling all the PA registers in turn. Each
device must have a unique Page Address value stored in
its PA register, or contention results. After all the PA
registers are filled, the entire string is reset through the
Control register, which does not change the values stored
in the individual PA registers. After the reset, the Device
Select registers usually are set to FFFFH to enable
operation in Case 1 of Table 4 on page 12. The Control
registers and the Segment Control registers are then set to
their normal operating values for the application.
Table 5 shows an example of code that initializes a
daisy-chained string of LANCAM devices. The
initialization example shows how to set the Page Address
registers of each of the devices in the chain through the
use of the Set Full Flag instruction, and how the Control
registers and Segment counters of all the LANCAM
devices are set for a typical application. Each Page
Address register must contain a unique value (not FFFFH)
to prevent bus contention.
For typical daisy chain operation, data is loaded into the
Comparand registers of all the devices in a string
simultaneously by setting DS=FFFFH. Since reading is
prohibited when DS=FFFFH (except for the device with a
match), for a diagnostic operation you need to select a
specific device by setting DS=PA for the desired device to
be able to read from it. Refer to Table 4 on page 12 for
preconditions for reading and writing. Initialization for a
single LANCAM is similar. The Device Select register in
this case is usually set to equal the Page Address register
for normal operations. Also, the dedicated /MA flag output
can be used instead of /MF, allowing /EC to be tied HIGH.
Table 5: Initialization Routine Example
Cycle Type
Op-Code
Control Bus
Comments
Notes
on DQ Bus
/E
/C
M
/W /EC
Command read
Command write
Command write
Command write
Command write
Command write
Command write
Command write
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Clear power-up anomalies
Target Device Select register to disable local device selection.
Disable Device Select feature.
Target Control register for reset.
Causes Reset.
Target Page Address register to set page for cascaded operation.
Page Address value.
Set Full flag; allows access to next device (repeat previous
two cycles plus this one for each device in chain.
Target Control register for reset of Full flags, but not Page address.
Causes Reset.
Target Control register for initial values.
Control register value.
Target Segment Count Control register
Set both Segment counters to write to Segment 1, 2, and 3, and read from
Segment 0.
TCO DS
FFFFH
TCO CT
0000H
TCO PA
nnnnH
SFF
1
2
2
2,3
Command write
Command write
Command write
Command write
Command write
Command write
TCO CT
0000H
TCO CT
8040H
TCO SC
3808H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
1
1
4
4
4
Command write
SPS M@HM
L
L
L
H
Set Data reads from Segment 0 of the Highest-Priority match
Notes:
1.
Toggling the /RESET pin generates the same effect as this reset of the Control register, but good programming practice dictates a software reset for
initialization to account for all possible prior conditions.
2.
3.
This instruction may be omitted for a single LANCAM application.
The last SFF causes the /FF pin in the last chip in a daisy chain to go LOW. In a daisy chain, DS needs to be set equal to PA to read out a
particular chip prior to a match condition.
4.
A typical LANCAM control environment: Enable match flag; Enable full flag; 48 CAM bits, 16 RAM bits; Disable comparison masking; and
Enable address increment. See Table on page 23 for Control Register bit assignments
Rev. 5.1
17
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