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MU9C1480BF-90TAI 参数 Datasheet PDF下载

MU9C1480BF-90TAI图片预览
型号: MU9C1480BF-90TAI
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 1KX64, 90ns, CMOS, PQFP44]
分类和应用: 双倍数据速率静态存储器内存集成电路
文件页数/大小: 32 页 / 236 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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LANCAM B Family  
Instruction Set Summary  
INSTRUCTION SET SUMMARY  
Mnemonic Format: INS dst, src[msk], val  
Instruction: Select Persistent Destination (continued)  
Operation  
Mnemonic  
Op-Code  
012EH  
016EH  
01AEH  
012FH  
016FH  
01AFH  
0134H  
0174H  
01B4H  
0135H  
0175H  
01B5H  
0136H  
0176H  
01B6H  
0137H  
0177H  
01B7H  
INS: Instruction mnemonic  
dst: Destination of the data  
src: Source of the data  
msk: Mask register used  
val: Validity condition set at the location written  
Mem. at Highest-Prio. Match, Skip  
Masked by MR1  
SPD M@HM,S  
SPD M@HM[MR1],S  
SPD M@HM[MR2],S  
SPD M@HM,R  
Masked by MR2  
Mem. at High.-Prio. Match, Random  
Masked by MR1  
SPD M@HM[MR1],R  
SPD M@HM[MR2],R  
SPD M@NF,V  
Instruction: Select Persistent Source  
Masked by MR2  
Mem. at Next Free Addr., Valid  
Masked by MR1  
Operation  
Mnemonic  
SPS CR  
Op-Code  
0000H  
0001H  
0002H  
0004H  
0804H  
0005H  
SPD M@NF[MR1],V  
SPD M@NF[MR2],V  
SPD M@NF,E  
Comparand Register  
Mask Register 1  
Masked by MR2  
SPS MR1  
Mem. at Next Free Addr., Empty  
MaskedbyMR1  
Mask Register 2  
SPS MR2  
SPD M@NF[MR1],E  
SPD M@NF[MR2],E  
SPD M@NF,S  
Memory Array at Addr. Reg.  
Memory Array at Address  
Mem. at Highest-Priority Match  
SPS M@[AR]  
SPS M@aaaH  
SPS M@HM  
MaskedbyMR2  
Mem. at Next Free Addr., Skip  
Masked by MR1  
SPD M@NF[MR1],S  
SPD M@NF[MR2],S  
SPD M@NF,R  
Masked by MR2  
Mem. at Next Free Addr., Random  
Masked by MR1  
Instruction: Select Persistent Destination  
SPD M@NF[MR1],R  
SPD M@NF[MR2],R  
Masked by MR2  
Operation  
Mnemonic  
Op-Code  
0100H  
0140H  
0180H  
0108H  
0110H  
0124H  
0164H  
01A4H  
0125H  
0165H  
01A5H  
0126H  
0166H  
01A6H  
0127H  
0167H  
01A7H  
0924H  
0964H  
09A4H  
0925H  
0965H  
09A5H  
0926H  
0966H  
09A6H  
0927H  
0967H  
09A7H  
012CH  
016CH  
01ACH  
012DH  
016DH  
01ADH  
Comparand Register  
Masked by MR1  
SPD CR  
SPD CR[MR1]  
Instruction: Temporary Command Override  
Masked by MR2  
SPD CR[MR2]  
Operation  
Mnemonic  
TCO CT  
TCO PA  
TCO SC  
TCO NF  
TCO AR  
TCO DS  
TCO PS  
TCO PD  
Op-Code  
0200H  
0208H  
0210H  
0218H  
0220H  
0228H  
0230H  
0238H  
Mask Register 1  
SPD MR  
Mask Register 2  
SPD MR2  
Control Register  
Mem. at Addr. Reg. set Valid  
Masked by MR1  
SPD M@[AR],V  
Page Address Register  
Segment Control Register  
Read Next Free Address  
Address Register  
SPD M@[AR][MR1],V  
SPD M@[AR][MR2],V  
SPD M@[AR],E  
Masked by MR2  
Mem. at Addr. Reg. set Empty  
Masked by MR1  
SPD M@[AR][MR1],E  
SPD M@[AR][MR2],E  
SPD M@[AR],S  
Device Select Register  
Read Persistent Source  
Read Persistent Destination  
Masked by MR2  
Mem. at Addr. Reg. set Skip  
Masked by MR1  
SPD M@[AR][MR1],S  
SPD M@[AR][MR2],S  
SPD M@[AR],R  
Masked by MR2  
Instruction: Data Move  
Mem. at Addr.Reg. set Random  
Masked by MR1  
SPD M@[AR][MR1],R  
SPD M@[AR][MR2],R  
SPD M@aaaH,V  
Operation  
Mnemonic  
Op-Code  
Masked by MR2  
Comparand Register from:  
No Operation  
Memory at Address set Valid  
Masked by MR1  
NOP  
0300H  
0301H  
0302H  
0304H  
0344H  
0384H  
0B04H  
0B44H  
0B84H  
0305H  
0345H  
0385H  
SPD M@aaaH[MR1],V  
SPD M@aaaH[MR2],V  
SPD M@aaaH,E  
Mask Register 1  
MOV CR,MR1  
Masked by MR2  
Mask Register 2  
MOV CR,MR2  
Memory at Address set Empty  
Masked by MR1  
Memory at Address Reg.  
Masked by MR1  
MOV CR,[AR]  
SPD M@aaaH[MR1],E  
SPD M@aaaH[MR2],E  
SPD M@aaaH,S  
MOV CR,[AR][MR1]  
MOV CR,[AR][MR2]  
MOV CR,aaaH  
Masked by MR2  
Masked by MR2  
Memory at Address set Skip  
Masked by MR1  
Memory at Address  
Masked by MR1  
SPD M@aaaH[MR1],S  
SPD M@aaaH[MR2],S  
SPD M@aaaH,R  
MOV CR,aaaH[MR1]  
MOV CR,aaaH[MR2]  
MOV CR,HM  
Masked by MR2  
Masked by MR2  
Memory at Address set Random  
Masked by MR1  
Mem. at Highest-Prio. Match  
MaskedbyMR1  
SPD M@aaaH[MR1],R  
SPD M@aaaH[MR2],R  
SPD M@HM,V  
MOV CR,HM[MR1]  
MOV CR,HM[MR2]  
Masked by MR2  
MaskedbyMR2  
Mem. at Highest-Prio. Match, Valid  
Masked by MR1  
Mask Register 1 from:  
Comparand Register  
No Operation  
SPD M@HM[MR1],V  
SPD M@HM[MR2],V  
SPD M@HM,E  
MOV MR1,CR  
NOP  
0308H  
0309H  
030AH  
030CH  
0B0CH  
030DH  
Masked by MR2  
Mem. at Highest-Prio. Match, Emp.  
Masked by MR1  
Mask Register 2  
MOV MR1,MR2  
MOV MR1,[AR]  
MOV MR1,aaaH  
MOV MR1,HM  
SPD M@HM[MR1],E  
SPD M@HM[MR2],E  
Memory at Address Reg.  
Memory at Address  
Mem. at Highest-Prio. Match  
Masked by MR2  
20  
Rev. 5.2  
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