LANCAM B Family
Instruction Set Summary
Instruction Cycle Lengths
Table 6: Instruction Cycle Lengths
Cycle
Length
Cycle Type
Command Read
Command Write
Data Write
Data Read
MOV reg, reg (except -70)
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
Comparand register
(not last segment)
Mask register
Short
(not last segment)
SBR, RSC
NOP (except -70)
SFT (8480B)
MOV reg, mem
MOV reg, reg (-70)
TCO CT (reset)
VBC (NFA invalid)
SFT (except 8480B)
NOP (-70)
Status register or
16-bit register Sheets
Memory array
(NFA invalid)
Comparand register
Mask register
Medium
MOV mem, reg
TCO CT (non-reset, HMA valid)
Memory array
(NFA valid)
Memory array
CMP
SFF
VBC (NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
Long
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics section under the
tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as the source or destination), the first
cycle is short, and the second cycle is the length given.
22
Rev. 5.2
MUSIC [ MUSIC SEMICONDUCTORS ]
