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MU9C1480BF-90TAI 参数 Datasheet PDF下载

MU9C1480BF-90TAI图片预览
型号: MU9C1480BF-90TAI
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 1KX64, 90ns, CMOS, PQFP44]
分类和应用: 双倍数据速率静态存储器内存集成电路
文件页数/大小: 32 页 / 236 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Instruction Set Descriptions  
LANCAM B Family  
Instruction: Validity Bit Control (VBC)  
Binary Op-Code: 0000 f100 00dd dvvv  
An RSC instruction resets the Segment Control register  
count values for both the Destination and Source counters  
to the original Start limits.  
f
Address Field flag  
ddd  
vvv  
Destination of data  
Validity setting for Memory location  
The Shift instructions shift the designated register one bit  
right or left. The right and left limits for shifting are  
determined by the CAM/RAM partitioning set in the  
The VBC instruction sets the Validity bits at the selected  
memory locations to the selected state. This feature can be  
used to find all valid entries by using a repetitive sequence  
of CMP V through a mask of all 1s followed by a VBC  
HM, S. If the VBC target is aaaH, the Address register is  
set to “aaaH.” For VBC instructions to or from aaaH or  
[AR], the Address register increments or decrements from  
that value after the operation completes, as set in the  
Control register.  
Control register. The Comparand register is  
a
barrel-shifter, and for the example of a device set to 64 bits  
of CAM executing a Shift Comparand Right instruction,  
bit 0 is moved to bit 63, bit 1 is moved to bit 0, and bit 63  
is moved to bit 62. For a Shift Comparand Left instruction,  
bit 63 is moved to bit 0, bit 0 is moved to bit 1, and bit 62  
is moved to bit 63. MR2 acts as a sliding mask, where for  
a Shift Right instruction bit 1 is moved to bit 0, while bit 0  
“falls off the end,” and bit 63 is replicated to bit 62. For a  
Shift Mask Left instruction, bit 0 is replicated to bit 1, bit  
62 is moved to bit 63, and bit 63 “falls off the end.” With  
shorter width CAM fields, the bit limits on the right or left  
move to match the width of CAM field.  
Instruction: Compare (CMP)  
Binary Op-Code: 0000 0101 0000 0vvv  
vvv  
Validity condition  
A CMP V, S, or R instruction forces a Comparison of  
Valid, Skipped, or Random entries against the Comparand  
register through a Mask register, if one is selected. During  
a CMP E instruction, the compare is only done on the  
Validity bits and all data bits are automatically masked.  
Instruction: Set Full Flag (SFF)  
Binary Op-Code: 0000 0111 0000 0000  
The SFF instruction is a special instruction used to force  
the Full flag LOW to permit setting the Page Address  
register in vertically cascaded systems.  
Instruction: Special Instructions  
Binary Op-Code: 0000 0110 00dd drrr  
Instruction: No Operation (NOP)  
ddd  
rrr  
Target resource  
Operation  
Binary Op-Code: 0000 0011 0000 0000  
The NOP (No-OP) belongs to the MOV instructions,  
where a register is moved to itself. No change occurs  
within the device. This instruction is useful in unlocking  
the daisy chain in Standard mode.  
These instructions are a special set for the LANCAM to  
accommodate the added features over the MU9C1480.  
Two alternate sets of configuration registers can be  
selected by using the Select Foreground and Select  
Background Registers instructions. These registers are the  
Control, Segment Control, Address, Mask Register 1, and  
the PS and PD registers.  
Rev. 5.1  
19  
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