Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Port Signals
When the PUPE bit in the PUCR register is set, PE7 and PE[3:0] are
pulled up by active devices.
Neither port E nor DDRE is in the map in peripheral mode; neither is in
the internal map in expanded modes with EME set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
3.6.4 Port G
Port G pins are used for key wake-ups that can be used with the pins
configured as inputs or outputs. The key wake-ups are triggered with a
falling edge signal (KWPG). An interrupt is generated if the
corresponding bit is enabled (KWIEG). If any of the interrupts is not
enabled, the corresponding pin can be used as a general purpose I/O
pin. Refer to I/O Ports with Key Wake-up.
Register DDRG determines pin direction of port G when used for
general-purpose I/O. When DDRG bits are set, the corresponding pin is
configured for output. On reset the DDRG bits are cleared and the
corresponding pin is configured for input.
Port PGUPD determines what type of resistive load is used for port G
input pins when PUPG bit is set in the PUCR register. When PGUPD pin
is low, it loads a pull-down in all port G input pins. When PGUPD pin is
high, it loads a pull-up in all port G input pins.
In 80-pin version, the PGUPD is connected internally to VDD. The PG4
will have a pull-up. All port G pins should either be defined as outputs or
have their pull-ups enabled.
Setting the RDPG bit in register RDRIV causes all port G outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Pinout and Signal Descriptions
55
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MOTOROLA [ MOTOROLA ]
