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XC68HC912D60FU8 参数 Datasheet PDF下载

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型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Pinout and Signal Descriptions  
Table 3-2. 68HC(9)12D60 Signal Description Summary  
Pin Number  
Pin Name  
Description  
80-pin  
112-pin  
Provides a means of requesting asynchronous nonmaskable interrupt  
requests after reset initialization  
XIRQ  
40  
56  
Single-wire background interface pin is dedicated to the background debug  
function. During reset, this pin determines special or normal operating  
mode. Pin function TAGHI used in instruction tagging. See Development  
Support.  
SMODN/BK  
GD/TAGHI  
15  
23  
PW[3:0]  
SS  
80, 1–3  
70  
112, 1–3 Pulse Width Modulator channel outputs.  
Slave select output for SPI master mode, input for slave mode or master  
96  
mode.  
SCK  
SDO/MOSI  
SDI/MISO  
TxD1  
69  
68  
67  
66  
65  
64  
63  
95  
94  
93  
92  
91  
90  
89  
Serial clock for SPI system.  
Master out/slave in pin for serial peripheral interface  
Master in/slave out pin for serial peripheral interface  
SCI1 transmit pin  
RxD1  
SCI1 receive pin  
TxD0  
SCI0 transmit pin  
RxD0  
SCI0 receive pin  
14–11,  
7–4  
Pins used for input capture and output compare in the timer and pulse  
accumulator subsystem.  
IOC[7:0]  
AN1[7:0]  
AN0[7:0]  
18–15, 7–4  
84/82/80/78/  
76/74/72/70  
N/A  
Analog inputs for the analog-to-digital conversion module 1  
Analog inputs for the analog-to-digital conversion module 0  
83/81/79/77/  
75/73/71/69  
60–53  
TxCAN  
RxCAN  
72  
73  
104  
105  
MSCAN transmit pin  
MSCAN receive pin  
8 (KWG4  
only)  
Key wake-up and general purpose I/O; can cause an interrupt when an input  
transitions from high to low. On 80-pin QFP all 8 I/O should be initialised.  
KWG[6:0]  
PGUPD  
9–11, 19–22  
13  
(1)  
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.  
24(KWH4  
only)  
32–35,  
49–52  
Key wake-up and general purpose I/O; can cause an interrupt when an input  
transitions from high to low. On 80-pin QFP all 8 I/O should be initialised.  
KWH[7:0]  
PHUPD  
(2)  
41  
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.  
1. In the 80-pin version PGUPD is connected internally to VDD  
2. In the 80-pin version PHUPD is connected internally to VSS  
Advance Information  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
52  
Pinout and Signal Descriptions  
For More Information On This Product,  
Go to: www.freescale.com  
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