Freescale Semiconductor, Inc.
Appendix: 68HC912D60A Flash EEPROM
Operation
22.7 Operation
The Flash EEPROM can contain program and data. On reset, it can
operate as a bootstrap memory to provide the CPU with internal
initialization information during the reset sequence.
22.7.1 Bootstrap Operation Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by
fetching the first program address from address $FFFE.
22.7.2 Normal Operation
The Flash EEPROM allows a byte or aligned word read in one bus cycle.
Misaligned word read require an additional bus cycle. The Flash
EEPROM array responds to read operations only. Write operations are
ignored.
22.7.3 Program/Erase Operation
An unprogrammed Flash EEPROM bit has a logic state of one. A bit
must be programmed to change its state from one to zero. Erasing a bit
returns it to a logic one. The Flash EEPROM has a minimum
program/erase life of 100 cycles. Programming or erasing the Flash
EEPROM is accomplished by a series of control register writes.
Programming is restricted to aligned word at a time as determined by
internal signal SZ8 and ADDR[0]. The Flash EEPROM must first be
completely erased prior to programming final data values.
Programming and erasing of Flash locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed t
maximum (40µs).
FPGM
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
403
Appendix: 68HC912D60A Flash EEPROM
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