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Table 19-1I. PIPE Decoding
(1)
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock
IPIPE[1:0]
0:0
Mnemonic
—
Meaning
No Movement
Latch Data From Bus
0:1
LAT
1:0
ALD
Advance Queue and Load From Bus
1:1
ALL
Advance Queue and Load From Latch
(2)
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock
IPIPE[1:0]
0:0
Mnemonic
—
Meaning
No Start
0:1
INT
Start Interrupt Sequence
Start Even Instruction
Start Odd Instruction
1:0
1:1
SEV
SOD
1. Refers to data that was on the bus at the previous E falling edge.
2. Refers to bus cycle starting at this E falling edge.
Program information is fetched a few cycles before it is used by the CPU.
In order to monitor cycle-by-cycle CPU activity, it is necessary to
externally reconstruct what is happening in the instruction queue.
Internally the MCU only needs to buffer the data from program fetches.
For system debug it is necessary to keep the data and its associated
address in the reconstructed instruction queue. The raw signals required
for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and
status signals IPIPE[1:0].
The instruction queue consists of two 16-bit queue stages and a holding
latch on the input of the first stage. To advance the queue means to
move the word in the first stage to the second stage and move the word
from either the holding latch or the data bus input buffer into the first
stage. To start even (or odd) instruction means to execute the opcode in
the high-order (or low-order) byte of the second stage of the instruction
queue.
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68HC(9)12D60 — Rev 4.0
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