Freescale Semiconductor, Inc.
Development Support
Figure 19-2 shows the host receiving a logic one from the target
68HC(9)12D60 MCU. Since the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host
holds the BKGD pin low long enough for the target to recognize it (at
least two target B cycles). The host must release the low drive before the
target MCU drives a brief active-high speed-up pulse seven cycles after
the perceived start of the bit time. The host should sample the bit level
about ten cycles after it started the bit time.
B CLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
HOST SAMPLES
BKGD PIN
Figure 19-3. BDM Target to Host Serial Bit Timing (Logic 0)
Figure 19-3 shows the host receiving a logic zero from the target
68HC(9)12D60 MCU. Since the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The
host initiates the bit time but the target 68HC(9)12D60 finishes it. Since
the target wants the host to receive a logic zero, it drives the BKGD pin
low for 13 B-clock cycles, then briefly drives it high to speed up the rising
edge. The host samples the bit level about ten cycles after starting the
bit time.
Advance Information
342
68HC(9)12D60 — Rev 4.0
MOTOROLA
Development Support
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA [ MOTOROLA ]
