Freescale Semiconductor, Inc.
Advance Information — 68HC(9)12D60
Section 19. Development Support
19.1 Contents
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
19.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
19.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .339
19.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
19.6 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
19.2 Introduction
Development support involves complex interactions between
68HC(9)12D60 resources and external development systems. The
following section concerns instruction queue and queue tracking signals,
background debug mode, and instruction tagging.
19.3 Instruction Queue
The CPU12 instruction queue provides at least three bytes of program
information to the CPU when instruction execution begins. The CPU12
always completely finishes executing an instruction before beginning to
execute the next instruction. Status signals IPIPE[1:0] provide
information about data movement in the queue and indicate when the
CPU begins to execute instructions. This makes it possible to monitor
CPU activity on a cycle-by-cycle basis for debugging. Information
available on the IPIPE[1:0] pins is time multiplexed. External circuitry
can latch data movement information on rising edges of the E-clock
signal; execution start information can be latched on falling edges. Table
19-1 shows the meaning of data on the pins.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Development Support
337
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