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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Motorola Interconnect Bus  
Biphase coding  
16.3.1 The push field  
The push field consists of a start bit, a push synchronization bit, a push  
data field and a push address field. The start consists of three time slots  
having the dominant logical state ‘0’. The start marks the beginning of  
the message frame by violation of the rule of the Manchester code. The  
push synchronization bit consists of a biphase coded ‘0’. Biphase coding  
will be discussed later. The push data field consists of five bits of biphase  
coded data. The push address consists of three bits of biphase coded  
data. Data and address are written to the lower byte of the SCI data  
register (SC0DRL). The push data occupies the lower five bits and the  
push address occupies the upper three bits of the register.  
16.3.2 The pull field  
The pull field consists of a pull synchronization bit, a pull data field and  
an end of frame. The pull synchronization bit is a biphase coded ‘1’ and  
is initiated by the MCU during the time slot after the last address bit of  
the push field. The pull data field consists of an NRZ coded transmission,  
each bit taking one time slot. Once shifted in, the pull data is stored in  
the lower byte of the SCI data register (SC0DRL). The end-of-frame field  
is a square wave signal having a typical frequency of 20kHz ± 1%  
tolerance (i.e. the bit rate of the push field) when the data sent to the  
selected device is valid.  
16.4 Biphase coding  
Manchester biphase L coding is used for the push field bits. Each bit  
requires two time slots to encode the logic value of the bit. This encoding  
allows the detection of a single error at the time slot level. Bits are  
encoded as follows:  
0 = In the first time slot, the logic level is set to one, followed by a  
logic level zero in the second time slot.  
1 = In the first time slot, the logic level is set to zero, followed by a  
logic level one in the second time slot.  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
Advance Information  
Motorola Interconnect Bus  
265  
For More Information On This Product,  
Go to: www.freescale.com  
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