Freescale Semiconductor, Inc.
Multiple Serial Interface
Serial Peripheral Interface (SPI)
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
SP0DR — SPI Data Register
$00D5
Read anytime (normally only after SPIF flag set). Write anytime (see
WCOL write collision flag).
Reset does not affect this address.
This 8-bit register is both the input and output register for SPI data.
Reads of this register are double buffered but writes cause data to be
written directly into the serial shifter. In the SPI system the 8-bit data
register in the master and the 8-bit data register in the slave are linked
by the MOSI and MISO wires to form a distributed 16-bit register. When
a data transfer operation is performed, this 16-bit register is serially
shifted eight bit positions by the SCK clock from the master so the data
is effectively exchanged between the master and the slave. Note that
some slave devices are very simple and either accept data from the
master without returning data to the master or pass data to the master
without requiring data from the master.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Multiple Serial Interface
259
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MOTOROLA [ MOTOROLA ]
