Freescale Semiconductor, Inc.
Multiple Serial Interface
Serial Peripheral Interface (SPI)
15.5.5 Register Descriptions
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to Operating Modes
and Resource Mapping.
Bit 7
SPIE
0
6
SPE
0
5
SWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SSOE
0
Bit 0
LSBF
0
RESET:
SP0CR1 — SPI Control Register 1
$00D0
Read or write anytime.
SPIE — SPI Interrupt Enable
0 = SPI interrupts are inhibited
1 = Hardware interrupt sequence is requested each time the SPIF
or MODF status flag is set
SPE — SPI System Enable
0 = SPI internal hardware is initialized and SPI system is in a low-
power disabled state.
1 = PS[4:7] are dedicated to the SPI function
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
SWOM — Port S Wired-OR Mode
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
outputs
MSTR — SPI Master/Slave Mode Select
0 = Slave mode
1 = Master mode
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Multiple Serial Interface
255
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA [ MOTOROLA ]
