Freescale Semiconductor, Inc.
Multiple Serial Interface
Serial Peripheral Interface (SPI)
MCU P CLOCK
(SAME AS E RATE)
S
MISO
PS4
M
M
S
DIVIDER
MOSI
PS5
8-BIT SHIFT REGISTER
READ DATA BUFFER
÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256
SP0DR SPI DATA REGISTER
SELECT
LSBF
SHIFT CONTROL LOGIC
PIN
CONTROL
LOGIC
CLOCK
SCK
PS6
S
CLOCK
LOGIC
SP0BR SPI BAUD RATE REGISTER
M
SS
PS7
MSTR
SPE
SPI CONTROL
SWOM
SP0SR SPI STATUS REGISTER
SP0CR1 SPI CONTROL REGISTER 1
SP0CR2 SPI CONTROL REGISTER 2
SPI
INTERRUPT
REQUEST
INTERNAL BUS
Figure 15-3. Serial Peripheral Interface Block Diagram
A clock phase control bit (CPHA) and a clock polarity control bit (CPOL)
in the SP0CR1 register select one of four possible clock formats to be
used by the SPI system. The CPOL bit simply selects non-inverted or
inverted clock. The CPHA bit is used to accommodate two
fundamentally different protocols by shifting the clock by one half cycle
or no phase shift.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
251
Multiple Serial Interface
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