Freescale Semiconductor, Inc.
Multiple Serial Interface
Serial Peripheral Interface (SPI)
Transfer
SCK (CPOL=0)
SCK (CPOL=1)
Begin
End
SAMPLE I
(MOSI/MISO)
CHANGE O
(MOSI pin)
CHANGE O
(MISO pin)
SEL SS (O)
(Master only)
SEL SS (I)
t
t
t
t
L
L
T
I
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB Minimum 1/2 SCK
for t , t , t
MSB
T
l
L
Figure 15-5. SPI Clock Format 1 (CPHA = 1)
15.5.3 SS Output
Available in master mode only, SS output is enabled with the SSOE bit
in the SP0CR1 register if the corresponding DDRS is set. The SS output
pin will be connected to the SS input pin of the external slave device. The
SS output automatically goes low for each transmission to select the
external device and it goes high during each idling state to deselect
external devices.
Table 15-3. SS Output Selection
DDS7
SSOE
Master Mode
SS Input with MODF Feature
Reserved
General-Purpose Output
SS Output
Slave Mode
SS Input
SS Input
SS Input
SS Input
0
0
1
1
0
1
0
1
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
253
Multiple Serial Interface
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