Freescale Semiconductor, Inc.
Multiple Serial Interface
Serial Communication Interface (SCI)
MCLK
DIVIDER
BAUD RATE
CLOCK
SCI TRANSMITTER
MSB
10-11 Bit SHIFT REG
LSB
PARITY
GENERATOR
Rx Baud Rate
Tx Baud Rate
TxD BUFFER/SCxDRL
SCxBD/SELECT
TxD
SCxCR1/SCI CTL 1
TxMTR CONTROL
SCxCR2/SCI CTL 2
DATA BUS
SCxSR1/INT STATUS
INT REQUEST LOGIC
RxD
SCI RECEIVER
TO
INTERNAL
LOGIC
PARITY
DETECT
DATA RECOVERY
MSB
LSB
10-11 BIT SHIFT REG
TxD BUFFER/SCxDRL
SCxCR1/SCI CTL 1
WAKE-UP LOGIC
SCxSR1/INT STATUS
SCxCR2/SCI CTL 2
INT REQUEST LOGIC
Figure 15-2. Serial Communications Interface Block Diagram
15.4.1 Data Format
The serial data format requires the following conditions:
• An idle-line in the high state before transmission or reception of a
message.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Multiple Serial Interface
239
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