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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Multiple Serial Interface  
BTST — Reserved for test function  
BSPL — Reserved for test function  
BRLD — Reserved for test function  
Bit 7  
LOOPS  
0
6
WOMS  
0
5
RSRC  
0
4
M
0
3
WAKE  
0
2
ILT  
0
1
PE  
0
Bit 0  
PT  
0
RESET:  
SC0CR1/SC1CR1 — SCI Control Register 1  
$00C2/$00CA  
Read or write anytime.  
LOOPS — SCI LOOP Mode/Single Wire Mode Enable  
0 = SCI transmit and receive sections operate normally.  
1 = SCI receive section is disconnected from the RXD pin and the  
RXD pin is available as general purpose I/O. The receiver input is  
determined by the RSRC bit. The transmitter output is controlled  
by the associated DDRS bit. Both the transmitter and the receiver  
must be enabled to use the LOOP or the single wire mode.  
If the DDRS bit associated with the TXD pin is set during the LOOPS  
= 1, the TXD pin outputs the SCI waveform. If the DDRS bit  
associated with the TXD pin is clear during the LOOPS = 1, the TXD  
pin becomes high (IDLE line state) for RSRC = 0 and high impedance  
for RSRC = 1. Refer to Table 15-2.  
WOMS — Wired-Or Mode for Serial Pins  
This bit controls the two pins (TXD and RXD) associated with the SCIx  
section.  
0 = Pins operate in a normal mode with both high and low drive  
capability. To affect the RXD bit, that bit would have to be  
configured as an output (via DDS0/2) which is the single wire  
case when using the SCI. WOMS bit still affects general purpose  
output on TXD and RXD pins when SCIx is not using these pins.  
1 = Each pin operates in an open drain fashion if that pin is  
declared as an output.  
Advance Information  
242  
68HC(9)12D60 — Rev 4.0  
Multiple Serial Interface  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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