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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Multiple Serial Interface  
• A start bit (logic zero), transmitted or received, that indicates the  
start of each character.  
• Data that is transmitted or received least significant bit (LSB) first.  
• A stop bit (logic one), used to indicate the end of a frame. (A frame  
consists of a start bit, a character of eight or nine data bits and a  
stop bit.)  
• A BREAK is defined as the transmission or reception of a logic  
zero for one frame or more.  
• This SCI supports hardware parity for transmit and receive.  
15.4.2 SCI Baud Rate Generation  
The basis of the SCI baud rate generator is a 13-bit modulus counter.  
This counter gives the generator the flexibility necessary to achieve a  
reasonable level of independence from the CPU operating frequency  
and still be able to produce standard baud rates with a minimal amount  
of error. The clock source for the generator comes from the M Clock.  
Table 15-1. Baud Rate Generation  
Desired  
BR Divisor for BR Divisor for  
SCI Baud Rate  
M = 4.0 MHz  
M = 8.0 MHz  
4545  
2273  
833  
110  
300  
2273  
833  
417  
208  
104  
52  
600  
1200  
2400  
4800  
9600  
14400  
19200  
38400  
417  
208  
104  
52  
35  
26  
17  
13  
26  
13  
Advance Information  
240  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
Multiple Serial Interface  
For More Information On This Product,  
Go to: www.freescale.com  
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